Re: [TUHS] core - TUHS

19 Jun 2018

On 2018-06-18 14:17, Noel Chiappa wrote:
...
   The
"separate" bus for the semiconductor memory is just a second Unibus  
 Err, no. :-) There is a second UNIBUS, but... its source is a second port on
 the FASTBUS memory, the other port goes straight to the CPU. The other UNIBUS
 comes out of the CPU. It _is_ possible to join the two UNIBI together, but
 on machines which don't do that, the _only_ path from the CPU to the FASTBUS
 memory is via the FASTBUS. 
Ah. You and Ron are right. I am confused.

So there were some previous PDP-11 models who did not have their memory 
on the Unibus. The 11/45,50,55 accessed memory from the CPU not through 
the Unibus, but through the fastbus, which was a pure memory bus, as far 
as I understand. You (obviously) could also have memory on the Unibus, 
but that would be slower then.

Ah, and there is a jumper to tell which addresses are served by the 
fastbus, and the rest then go to the Unibus. Thanks, I had missed these 
details before. (To be honest, I have never actually worked on any of 
those machines.)

   Johnny

-- 
Johnny Billquist                  || "I'm on a bus
                                   ||  on a psychedelic trip
email: bqt(a)softjar.se             ||  Reading murder books
pdp is alive!                     ||  tryin' to stay hip" - B. Idol