On Fri, Sep 29, 2023, at 11:35 PM, Marc Donner wrote:
I infer from your inquiry that there is no formal
statement of the ISA for the machine. Is that correct?
The CPU itself is a standard off the shelf WE32200, which is thankfully very well
documented, so the ISA is not really an issue. The real thorny question is how everything
else is all hooked together. The interrupt controller, the IO buses, the DRAM controller,
and so on, are partly documented in the technical reference manual, but only at a very
high level, and with at least a few major inaccuracies. Detailed behavior like bus
timeouts, error conditions, and so on, are very poorly documented. I was only able to
infer how everything was connected on the 3B2/400 by reading the kernel source code to
understand what the various drivers expected to see, but the 3B2/700 has a very different
memory map and the kernel source code is missing. I have the system board schematics, but
there an awful lot of PALs, and no PAL truth tables.
-Seth
--
Seth Morabito * Poulsbo, WA *
https://loomcom.com/