On Mon, Dec 16, 2024 at 10:40:34AM -0500, Douglas McIlroy wrote:
> Does
anyone know whether there are implementations of mmap that
> do transparent file sharing? It seems to me that should be possible by
> making the buffer cache share pages with mmapping processes.
These days they all do. The POSIX rationale
says:
> ... When multiple processes map the same memory object, they can
> share access to the underlying data.
I don't see this language in the 2024 version of POSIX (IEEE Std 1003.1-2024).
Notice the weasel word "can". It is not
guaranteed that they will do so
automatically without delay. Apparently each process may have a physically
distinct copy of the data, not shared access to a single location.
The Linux man page mmap(2), for example, makes it very clear that mmap
has a cache-coherence problem, at least in that system. The existence
of msync(2) is a visible symptom of the problem.
Huh? What language are you talking about? msync(2) is about when
dirty data is written to stable storage (e.g., written back out to
disk). It works much like fsync(2).
There is a cache-coherency problem between what's in the buffer/page
cache (Linux has a unified page cache, so file-backed blocks are not
cached in the buffer cache; only the page cache) and O_DIRECT. Some
OS's will tell you that there is no coherency guarantees at all.
Linux will give a best-efforts attempt at coherency which is to say
that before doing an O_DIRECT read, any dirty pages will be written
out to disk before the O_DIRECT read is allowed to proceed, and before
doing an O_DIRECT write, any underlying pages in the page cache will
be invalidated. It is not 100% guaranteed to be coherent, and system
which try to mix simultaneous buffered and O_DIRECT I/O may not
necessarily get what they want.
However, if what you are talking about is multiple processes mmap'ing
the same file, they *will* get the same page in the page cache mapped
into the page tables, which means that writes by one process will be
immediately seen by another process (modulo CPU cache coherency
guarantees, of course; Intel is pretty good; with a weekly consistent
architecture like Alpha, your mileage may vary unless you know what
you are doing and write your assembly code accordingly).
Cheers,
- Ted