TUHS

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Re: [TUHS] PDP-11/70 SPL (was: Early non-Unix filesystems?)

by jnc＠mercury.lcs.mit.edu

> From: Johnny Billquist > It would also be interesting if anyone can come up with a good reason > why SPL should work that way. So that when doing: SPL 0 WAIT you don't lose by having the interrupt happen between the SPL and the WAIT? Noel

9 years, 1 month

Re: [TUHS] PDP-11/70 SPL (was: Early non-Unix filesystems?)

by Johnny Billquist

On 2016-03-27 03:50, Dave Horsfall<dave(a)horsfall.org> wrote: > > On Fri, 25 Mar 2016, Johnny Billquist wrote: > >>> > >Some instructions inhibit the "check for interrupts at the end of this >>> > >instruction" check. I'm most familiar with the 8080 EI instruction, >>> > >which enabled interrupts after the following instruction (so things >>> > >like EI;HLT didn't have a window). It seems the PDP-11 SPL behaves >>> > >the same. >> > >> >I don't think it should on the PDP-11, and the documentation do not >> >mention any such thing. > It most certainly did, at least on the 11/70 that I used... Do you have > experience otherwise? I do not have any experience either way. I have never checked this. I'm just saying that it don't make sense in my head, and the processor handbook do not describe such a property of SPL. But now that I know, I'm going to try and find out. It might be correct. I'm just surprised if so, since there is no technical need for SPL to act that way. And having SPL behave differently than all other instructions means extra work for the people who wrote the microcode. It would also be interesting if anyone can come up with a good reason why SPL should work that way. Johnny -- Johnny Billquist || "I'm on a bus || on a psychedelic trip email: bqt(a)softjar.se || Reading murder books pdp is alive! || tryin' to stay hip" - B. Idol

9 years, 1 month

Re: [TUHS] [GreenKeys] Teletype simulator? (fwd)

by Dave Horsfall

As attached, thanks to someone over on the RTTY list; not sure if it's exactly what he wanted. -- Dave Horsfall DTM (VK2KFU) "Those who don't understand security will suffer." ---------- Forwarded message ---------- Date: Sat, 26 Mar 2016 18:52:59 -0700 From: tony.podrasky To: Dave Horsfall <dave(a)horsfall.org> Subject: Re: [GreenKeys] Teletype simulator? (fwd) Hi Dave; Attached is my TTY test program. It is fairly simple. The only thing that might be tricky is the type of UAR/T you are using. Let me know if it compiles. regards, tony On 03/26/2016 06:33 PM, Dave Horsfall wrote: > On Fri, 25 Mar 2016, tony.podrasky wrote: > > > What do you mean, "a non-Windoze" TTY simulator? > > One that's in source form, not binary... > > > One of the programs I have takes e-mail and prints it on a 5-level ITA#2 > > machine. > > > > It is written in "C", and at such a low-level that it should compile on > > ANY thing that runs "C". > > Got a copy you can send me to pass on? > -- "I read somewhere that 77 percent of all the mentally ill live in poverty. Actually, I'm more intrigued by the 23 per cent who are apparently doing quite well for themselves." -Jerry Garcia

9 years, 1 month

Re: [TUHS] Early non-Unix filesystems?

by Johnny Billquist

On 2016-03-24 03:00, "Ron Natalie"<ron(a)ronnatalie.com> wrote: > >> >Closest I've ever been murdered was when I "accidentally" filled the local >> >11/70 with an uninterruptible instruction sequence." > SPL instruction. The PDP-11 was odd that while SPL was a "privileged" > instruction, rather that trapping if you did it in user mode, it just > "ignored" it. > Well, what it ignored was the actual change of the processor level. What > it still implemented was the side effect was that interrupts were locked out > until the next instruction fetch. > If you filled your instruction space up with SPLs you could lock up the > computer so that even the HALT key didn't work (you had to do a bus RESET). Ok. Color me stupid, but I don't get it. I totally do not understand how this locks anything out. It is the normal behavior of any instruction that interrupts are not recognized until the next instruction fetch. This is how the microcode works, and it is also pretty much the same in any processor today. Except for instructions that take a long time, and which can be interrupted in the middle, the context preserved, and the instruction restarted and continued, instructions are normally atomic. You cannot get interrupts in the middle of an instruction. Second, I cannot understand how filling the memory with SPL instructions (or any other instruction) can lock out the CPU. As noted, they are individual instructions. You still get a fetch between each instruction, at which point, interrupts will be recognized. Now, if you instead talked about actually raising the CPU to SPL 7, then I agree that no interrupts will happen. But that is because you essentially disabled interrupts. The front panel still works though. It is not handled like an interrupt, but it is true that it do interact with the processor states, and normally if you pull HALT, it will only halt when it's going to fetch the next instruction. You can, of course, also set the front panel switch for single microcode instruction, at which point the CPU will halt at the next microcode instruction instead, and you can single step the microcode as well. The one CPU I know you can sunset is the KA10 (PDP-10). I'm sure there are others, but I have never seen how this could be done on a PDP-11, so I'm most curious about this, and if you can provide more details I would be most interested. As I also happen to know where a PDP-11/70 is standing, I intend to test this out next I get close to it. As for the KA10 (I think it was the KA10, but it might have been the PDP-6), the problem is related to the indirect addressing feature. Since memory is 36 bits, but addresses only 18, you have plenty of bits to play with. And one of them is the indirect bit. And if you refer to a memory location that also have the indirect bit set, you get another memory access to get the actual content. The fun thing happens if you set the indirect bit, and give your own address. This is then an infinite memory reference. And the KA10 can not be broken out of that lookup. The only solution is to pull the power plug. The CPU is essentially stuck in one state, just tightly reading memory, and then repeating reading memory. Later PDP-10 models have an explicit check in the microcode in this loop to be able to break out of this. Sorry for the offtopic content. :-) Johnny -- Johnny Billquist || "I'm on a bus || on a psychedelic trip email: bqt(a)softjar.se || Reading murder books pdp is alive! || tryin' to stay hip" - B. Idol

9 years, 1 month

TTYs etc...

by Ronald Natalie

There is only one terminal that is explicitly (and unkindly) mentioned in the UNIX kernel. Leave poor tilde alone!

9 years, 1 month

Re: [TUHS] DEC filenames (was: Command-line options)

by Johnny Billquist

On 2016-03-26 20:43, Clem Cole<clemc(a)ccc.com> wrote: > > On Fri, Mar 25, 2016 at 11:09 PM, Charles Anthony < > charles.unix.pro(a)gmail.com> wrote: > >> >And Dec's RADIX-50, packing 3 characters into 16 bits. (IIRC the origin of >> >the 6.3 filenames. bit I can't document that.) > > Sort of.... before ASCII, DEC used a few other 5 bit codes that were > around such as baudot (look at the PDP-1/4 etc and KSR 28). RAD50 was a > natural scheme for storing file name and using bits efficiently. > > Which, of course, lead to the abomination of case folding - it's not a bug, > it's a feature 😂 > > RAD50 gave us the x.y file name form with the implied dot et al. 6.3 and > later 8.3 were natural directions from that coding. Using the .3 ext as a > type tag of course followed that naturally given that's all that was stored > in the disk "catalog." [And CP/M and PC/MS-DOS inherit that scheme - > including the case folding silliness even though by that time all keyboard > were upper and lower case and they stored the files in 8 bits]. Some other people already mentioned this, but... - SIXBIT. DEC might have used baudot in the very early machines, but I would say that SIXBIT dominated here for a long time. We see it both in the PDP-8, but also the PDP-6 and its follow ons. RAD50 was the natural extension of SIXBIT on a machine that did not have a word size that was a multiple of 6. The x.y filename, as well as the 6+3 pattern predate the PDP-11. I would say that in this area, the PDP-11 didn't come with anything new, but just made life more complicated. OS/8 for sure only have 6+2 filenames, but still in the x.y form. TOPS-10 have, I think, 6+3. And the Monitor (I think that was the name for the PDP-6 OS) was, I think, also 6+3. And it was all SIXBIT. And SIXBIT also give you the case folding. I say the PDP-11 complicated life just because DEC was already so much into having filenames stored more compact than normal text, and having a 6+3 pattern, so they came up with R50, which fits the bill, but it's more headache than it was worth, if you ask me. Since the PDP-11 have 8 bit bytes, it would have made much more sense to just store filenames as 8 bit bytes. It would have cost some more storage, but not that much. But it took time for DEC to realize that the space savings here were not really a good tradeoff. Old habits die hard, I guess. By the way, RSX (and early VMS) actually use 9+3 filenames. > UNIX of course, would put the "type" in the file itself (magic #) and force > the storing of the dot, but removed the strict mapping of name and type. > Having grown up in both systems, I see the value of each; but agree I think > I find UNIX's scheme better and lot more flexible. I think I agree on the point of having filenames in a free format. Not sure I really like storing the type in the file itself. So I'm sortof torn. Or rather, I would like to keep type separate from both. Johnny -- Johnny Billquist || "I'm on a bus || on a psychedelic trip email: bqt(a)softjar.se || Reading murder books pdp is alive! || tryin' to stay hip" - B. Idol

9 years, 1 month

PDP-7 Unix: The B compiler works

by Warren Toomey

We've got the B compiler working. Robert Swierczek gets all the credit. Cheers, Warren @ ls -l . 00004 drwr- 04 777 00050 dd 00003 drwr- 03 777 00340 system 00046 srwr- 01 014 00130 b_readme 00047 lrwr- 01 014 04065 bi.s 00050 lrwr- 01 014 02016 bl.s 00051 srwr- 01 014 00073 hello.b 00052 lrwr- 01 014 03450 ops.s 00045 drwr- 02 014 00110 . @ cat hello.b main $( write('He'); write('ll'); write('o,'); write(' W'); write('or'); write('ld'); write('!*n'); $) @ bc hello.b hello.s @ as ops.s bl.s hello.s bi.s I II ops.s bl.s hello.s bi.s @ a.out Hello, World!

9 years, 1 month

OT? Bow to UNIX Children of Macintosh...

by Ben Greenfield

Hey All, I just saw in another thread the statement their are no odd requests here. So I thought I would test that. The day NeXT took over Apple I read a page somewhere on the internet that started with line. Bow down to UNIX children of Macintosh... It then when on its Old Testament conquering tone about the new way of computing that was coming. Does anybody have any idea who wrote this or where to find it? Thanks, Ben

9 years, 1 month

Again about etymology: rc

by Rocky Hotas

Hello everyone, I am Rocky and this is my first message. Before starting, I would like to thank you for all the valuable informations and stories you post here. About the History of Unix, I was wondering with another guy why the rc script has that name. As many of you already know, and according to NetBSD, FreeBSD, OpenBSD (current) manual, "The rc utility is the command script which controls" the startup of various services, "and is invoked by init(8)" (from DESCRIPTION). "The rc command appeared in 4.0BSD" (from HISTORY). Words may slightly change between the three distributions, but the meaning and the informations provided are the same. So, the etymology of rc does not appear in the man pages. Do you know how to recover it? Do (or did) the letters rc have some meaning in this context? Cheers, Rocky

9 years, 1 month

Re: [TUHS] Early non-Unix filesystems?

by Johnny Billquist

On 2016-03-25 00:27, Milo Velimirovic wrote: > >> On Mar 24, 2016, at 6:06 PM, Johnny Billquist <bqt(a)update.uu.se> wrote: >> >> On 2016-03-24 23:50, Peter Jeremy wrote: >>> On 2016-Mar-24 11:17:18 +0100, Johnny Billquist <bqt(a)update.uu.se> wrote: >>>> It is the normal behavior of any instruction that interrupts are not >>>> recognized until the next instruction fetch. This is how the microcode >>>> works, and it is also pretty much the same in any processor today. >>> ... >>>> individual instructions. You still get a fetch between each instruction, >>>> at which point, interrupts will be recognized. >>> >>> Some instructions inhibit the "check for interrupts at the end of this >>> instruction" check. I'm most familiar with the 8080 EI instruction, >>> which enabled interrupts after the following instruction (so things like >>> EI;HLT didn't have a window). It seems the PDP-11 SPL behaves the same. >> >> I don't think it should on the PDP-11, and the documentation do not mention any such thing. >> There is a good reason the 8080 (and Z80, and others) have this property. The RETI instruction on these machines do not enable itnerrupts themselves, so just as you note, you need to both enable interrupts and return from interrupt atomically, or else you get into a mess. >> >> The PDP-11 RETI instruction changes the processor priority as a part of the instruction. You do not use SPL (whatever) before a RETI. >> Thus, it do not make sense that SPL on a PDP-11 would have this property. If if indeed do disable recognizing interrupts after an SPL, it sounds more like a bug. I guess I'll go and read the microcode so see if that mentions any of this, since I'm sortof into reading it anyway as I was trying to debug a problem on an 11/70 only a couple of months ago… > > The PDP-11 has no RETI instruction; it has a RTT (ReTurn from Trap) and a RTI (ReTurn from Interrupt) instructions, but you already knew that, right? In some cases it’s problem that it’s not possible to determine which is appropriate or correct to use. According to the PDP11 Architecture Handbook the difference between them is in what happens when the RTx instruction loads a PSW that has the T bit set and when it forces a Trace trap. RTI - immediate trap, RTT traps after the instruction following the RTT. Oops. Yes, it's RTI and RTT. But the names are beside the point, and so is the difference between these two. The point is that the instruction(s) do set the processor priority level, and you do not use SPL in combination with them, so it makes no sense to have SPL inhibit interrupts for any length at all. (And yes, I did know that.) Oh, and as far as RTT vs. RTI goes, not it's not hard to know which one you want. You want RTT for your debugger and RTI for everything else. The difference is about what happens after the return. With RTT, the T-bit trap will not trap until another instruction has executed. With RTI, you would never manage to step to the next instruction with the T-bit, since every time you returned, you'd get another trap. But I bet you knew that as well... ;-) Johnny -- Johnny Billquist || "I'm on a bus || on a psychedelic trip email: bqt(a)softjar.se || Reading murder books pdp is alive! || tryin' to stay hip" - B. Idol

9 years, 1 month

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