10 Aug
2018
10 Aug
'18
3:13 p.m.
On Fri, Aug 10, 2018 at 10:43 AM, Larry McVoy <lm(a)mcvoy.com> wrote:
The original SPARC CPU was 20K gates and was faster
than the 68020.
Yep... pretty clean design.
My guess is cheaper as well.
Maybe -- TI was the fab right? Moto's fabs were pretty good, not as good
at Intel in those days.
IIRC TI was still transitioning from BiPolar to CMOS, and most of the fab
capacity was still in their BiPolar area (somewhere along the line the
bought Nat Semi). As I understand from a buddy who as at TI at the time,
DSPs and SPARCs were driving the transistion. But they might not have been
there yet.
I was at Sun as they were making the
transition from 68K to SPARC and we all fought to get SPARC machines
because of performance.
Yeah, they kicked butt. Less is more and all that. Had us worried at
Stellar because we were doing custom (Gate Arrays). We had hit 22 MIPS,
if I recall Sparc was 4-6 range; but that was pretty darned good for a
single chip at the time.
I liked the 68K well enough, it was fairly nice in assembler (though
my heart belongs to the PDP-11 first, the National 32032 next, and
then the 68K for assembler). But the SPARC chips were just faster.
+1
althought I'd probably swap the 68K and 32032 because the National device
(which was pretty much a vax on a chip, as the 68k was an 11 on a chip),
was clean and cool, it was later in my life; so I knew the 68K better.
BTW: Stellar was a 'RISCy' 68K with support for Fortran (*i.e.*
indirection beyond pure load/store). We used to say all devices post
Dave's papers were RISC ;-) FWIW:
I never really thought much of the RISC chips, accept maybe the by the time
of the MIPS 4400 series; but then again they were were designed for
compiler writers.
And the whole RISC thing was a bit of marketing. John Coche never said
"reduce to the instruction set", he said "compile to (*i.e.* expose) the
microcode." Dave sort of missunderstood his message.
Clem
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