On Fri, Aug 10, 2018 at 3:44 AM, Bakul Shah <bakul(a)bitblocks.com> wrote: I agree.. I think you nailed it. FWIW: I used to commute to work with the Les Crudele, who was the lead HW guy on the 68000 (and later MIPS and few other things - pretty amazing guy).Les' stories of how Moto dropped the ball are classic. Frankly, think the 'failure' started with chip at the start. It was a skunkworks project in the back of a lab, and they had to hide the original mask charge. They borrowed time on a PDP-11/70 (running ISC's UNIX) to do their support. Tom Grunner told his bosses that they were playing with an idea and it was just a couple of guys, let them be. The hundreds were focused on the real product (6800 line), What's really interesting is that IBM and Moto were pretty tight at the time. MECL - Motorola Emitter Coupled Logic - had been designed by Moto for IBM for the System/360 and was licensed. When the original chip X-series chip (what would become the 68000) was fabbed, they sent 10 of them to a number of their partners (it did not have a number yet). IBM had them, as did we at Tektronix (and I've told the story of by cobbling together hacks on the Ritchie compiler to create something to emit what would become 68000 instructions in the summer of 1979 before it was announced). Les says that when IBM visited Austin to talk about a processor for their project, they had had the experimental chip running in the lab in NY/Conn. But Motorola marketing told them what they needed was the newly announced 6809 and that the device Les and team were making was just a test. No, plans for it. IBM insisted on a 16bit part (per the Gates recommendation discussed before and they knew others like Intel had them). Moto tried to show them the 16-bit extentions in the 6809. Les said, IBM kept asking, and asking about the 'other chip' but Moto management said it is not a product - the 6809 is. IBM would leave the Moto meeting, and the rest is history. BTW: the other story he tells is when Jobs did use the 68000 for what would become the Mac, Moto offered that base limit register MMU chip for free (which I've forgotten the number); but Jobs said they didn't want it, it would make the design too complicated. They were making a PC and did not need an MMU (remember the Xerox Alto's did not have either). The other thing of course is the hash they made of the 68000 instruction space with the Mac OS system traps fiasco. Then as Larry points out the CISC vs. RISC craze began, and the problem was that by the time the 88000; Intel had started to catch up in base performance. And the whole RISC vs. CISC thing was misunderstood -- economics won out. As I like to say, 'success' in the computer business is driven by economics as the high bit, not pure technology. Christensen's disruption theory explains it the best. The problem is that a new technology, particularly when it comes from within, is scary for an established firm, because it will erode the cash cow you already have. Moto was making big bucks with the 6800 and 6809 was the replacement -- that's what they had planned. The 68000 came from nowhere and not valued, so it was not given a chance. But the time they recognized its value, they had lost the important (economic) player (IBM). To be fair, at the time, I did not think Intel would be able to recover from the segmented log/short pointers issues of the 8086. The 386 was an awesome recovery from a technology standpoint, but it only came to be because of the economics of the PC. And by the way, it was also a back room solution when large numbers of the rest of the firm was working on new 'better' tech chasing the RISC chimera. BTW: Look at the missteps Intel made with architect -- i432, i860, i960, itianium. Interesting technology. As Larry said, Alpha was just amazing from DEC. But in the end, what mattered was economic volume. Better margins in all of these than the established tech, but they all lost in the end. It will be interesting to see if my firm realizes this we move into the future. High margins are something sr manager loves because it keeps profits up/the stock price high, until the disruption occurs..... then you are in trouble. ᐧ

On Fri, Aug 10, 2018 at 10:43 AM, Larry McVoy <lm(a)mcvoy.com> wrote: Yep... pretty clean design. Maybe -- TI was the fab right? Moto's fabs were pretty good, not as good at Intel in those days. IIRC TI was still transitioning from BiPolar to CMOS, and most of the fab capacity was still in their BiPolar area (somewhere along the line the bought Nat Semi). As I understand from a buddy who as at TI at the time, DSPs and SPARCs were driving the transistion. But they might not have been there yet. Yeah, they kicked butt. Less is more and all that. Had us worried at Stellar because we were doing custom (Gate Arrays). We had hit 22 MIPS, if I recall Sparc was 4-6 range; but that was pretty darned good for a single chip at the time. +1 althought I'd probably swap the 68K and 32032 because the National device (which was pretty much a vax on a chip, as the 68k was an 11 on a chip), was clean and cool, it was later in my life; so I knew the 68K better. BTW: Stellar was a 'RISCy' 68K with support for Fortran (*i.e.* indirection beyond pure load/store). We used to say all devices post Dave's papers were RISC ;-) FWIW: I never really thought much of the RISC chips, accept maybe the by the time of the MIPS 4400 series; but then again they were were designed for compiler writers. And the whole RISC thing was a bit of marketing. John Coche never said "reduce to the instruction set", he said "compile to (*i.e.* expose) the microcode." Dave sort of missunderstood his message. Clem ᐧ

Back when I was doing vision processing in a parallel way, I worked with the hardware guys to move from a 68010 to the 020 and then the 040. Each was a big step up in performance and we had little work to do in the software other than recompiling to get the better performance. And then I ran the vision algorithms on my Sparc desktop box (I think it was a SS10, maybe a SS20). And they ran about 30x faster. Same image, same results, 30x faster. So I spent some time to come up with a design that pulled the images from the camera directly into the Sparc host and with a little help from the hardware guys we had a board that would do that. So it came down to cost and performance. I loved the 68k processors and was very happy with them, but we could build custom frame grabbers cheaper and have the host do the work faster. David