31 Aug
2019
31 Aug
'19
9:38 a.m.
One thing I can think of is something like this:
IIRC 68k had 24 address bits. So with a 4K page size, you can have one level
pagetable. If the pagetable is in fast SRAM, may be 1 or 2 clock cyles would
be added. If you allow 2^N processes, you need 2^(12+N) entry page table. The
width of the table would depend on the number of 4K pages in the physical
memory. Context switch would be to simply set the 2^N bit process "base"
register. Going beyond 2^N you'd have to swap out a process. Each process can
then grow up to 16MB. I don't think a real translation lookaside buffer would
help much.
It would be interesting to see the actual details.
On Aug 30, 2019, at 7:57 PM, Clem cole
<clemc(a)ccc.com> wrote:
Btw. The issue with the 68k was Nick Tredenick’s original Microcode did not save enough
information during some of the faults. Les Crudele once told me, that it turns out he had
tried to fix it but there were a series of errors and some short cuts they used to fit it
in the store. They gave up trying to fix it as the part was purely skunkworks and they
could not respin it at the time. After it succeeded and were a real project, the
difference between the original and the 10 was Nick redid the microcode but they had made
a larger microstore - otherwise basically the same Si.
Sent from my PDP-7 Running UNIX V0 expect things to be almost but not quite.
> On Aug 30, 2019, at 10:46 PM, Clem cole <clemc(a)ccc.com> wrote:
>
> There was most definitely a TLB or as Dave called it ‘The TB’ ***
> Remember Dave Cane (Masscomp hw lead) was part of the 780, led the 750 and designed
the BI before he left dec. He was a bus and memory specialist
>
>
> *** west coast VS east coast training - calling it a TB vs a TLB.
>
> Sent from my PDP-7 Running UNIX V0 expect things to be almost but not quite.
>
>>> On Aug 30, 2019, at 9:13 PM, Bakul Shah <bakul(a)bitblocks.com> wrote:
>>>
>>> On Fri, 30 Aug 2019 20:58:13 -0400 Clem Cole <clemc(a)ccc.com> wrote:
>>>
>>> Actually not in lock step. They were independent. One was called the
>>> executor and the other the fixer. When a fault was detected the executor
>>> was sent wait stated while the fixer handled the fault and refilled the
>>> TLB. Once the TLB was set to instruction was allowed to complete. Btw
>>> when the 68010 was released the pals on the board were changed to allow the
>>> executor to actually take the fault and do something else while the fixer
>>> replaced the TLB entry
>>
>> As I remember, the issue with 68000 was that instructions were
>> not restartable so in case of accessing memory that didn't
>> exist, you couldn't take a segfault and do anything useful.
>> This is why you needed a second processor to deal with an
>> external MMU. There would have been no TLB unless you actually
>> added an external TLB -- but an external CAM would've been
>> very expensive. May be a direct map?
>>
>> What we did at Fortune was to utilize a 4 entry external map:
>> text, data, extra and stack. When a new function was invoked
>> it would do a 'probe'. If the probe caused a segfault, stack
>> was extended in the handler. The probe didn't have to be
>> restartable. So we didn't need a second 68k. This logic may
>> have been in the V7 port we started from.