27 Mar
2016
27 Mar
'16
4:05 p.m.
On 2016-03-27 03:50, Dave Horsfall<dave(a)horsfall.org> wrote:
On Fri, 25 Mar 2016, Johnny Billquist wrote:
I do not have any experience either way. I have never checked this. I'm
just saying that it don't make sense in my head, and the processor
handbook do not describe such a property of SPL. But now that I know,
I'm going to try and find out.
It might be correct. I'm just surprised if so, since there is no
technical need for SPL to act that way. And having SPL behave
differently than all other instructions means extra work for the people
who wrote the microcode.
It would also be interesting if anyone can come up with a good reason
why SPL should work that way.
Johnny
--
Johnny Billquist || "I'm on a bus
|| on a psychedelic trip
email: bqt(a)softjar.se || Reading murder books
pdp is alive! || tryin' to stay hip" - B. Idol
> > >Some instructions inhibit the
"check for interrupts at the end of this
> > >instruction" check. I'm most familiar with the 8080 EI
instruction,
> > >which enabled interrupts after the following instruction (so things
> > >like EI;HLT didn't have a window). It seems the PDP-11 SPL behaves
> > >the same.
>
>I don't think it should on the PDP-11, and the documentation do not
>mention any such thing.
It most certainly did, at least on the 11/70 that I
used... Do you have
experience otherwise?