18 Jan
2017
18 Jan
'17
1:55 a.m.
Ah, the notion of clock speed... For 75 years we have designed
circuits with a central clock. For the last 10 years, people have
gone to great length to make a billion transistors on a chip operate
in synchrony, using techniques that are getting sillier and sillier
and don't provide much benefit. For example, at lower voltages and
thinning wires, chips become dramatically more temperature sensitive,
so all kinds of guard bands and additional hardware gook is required
to make the chips function correctly. There are some very
interesting technologies that are not clock based, scale well, are low
power, and perform well over wide variations of voltage and
temperature, The problem is they would require a completely new
set of design tools, and the few players in this area don't want to
rock the boat.
It's not necessary to go that far, however. Our chip has no global
signals and will probably be faster than 6 GHz.
Steve
----- Original Message -----
From: "Tim Bradshaw" <tfb(a)tfeb.org>This doesn't mean that the
process
will continue: eventually you hit physics limits ('engineering' is
really a better term, but it has been so degraded by 'software
engineering' that I don't like to use it). Obviously we've already
hit those limits for clock speed (when?) and we might be close to them
for single-threaded performance in general: the current big (HPC big)
machine where I work has both lower clock speed than the previous
one and observed lower single-threaded performance as well, although
its a lot more scalable, at least in theory. The previous one was
POWER, and was I think the slightly mad very-high-clock-speed POWER
chip, which might turn out to be the high-water-mark of
single-threaded performance; the current one is x86.