16 Jul
2021
16 Jul
'21
6:11 p.m.
On Jul 16, 2021, at 6:56 AM, Larry McVoy <lm(a)mcvoy.com> wrote:
On Fri, Jul 16, 2021 at 09:00:58AM -0400, Theodore Y. Ts'o wrote:
This is somewhat h/w dependent. Ideally you want the h/w to
do some buffering for streaming at full speed so that you
don't need to take a per char or per packet interrupt. Hence
NS16550 which used a 16 char FIFO. AMD LANCE used a ring of
2^N buffer descriptors. Intel 82586 used a linked list -
don't recall if you had to make it a circular buffer. The
early 3COM controller didn't buffer more than a packet and
you had to copy it. As a contractor I did a couple of network
drivers for 3rd party hardware for SGI in late '80s & early
'90s. I don't recall any details now but in both cases the
h/w did buffer up a bunch. Once things are handed to s/w, you
have a lot more flexibility. Though I never liked the idea of
splitting a packet up in multiple mbufs!
The trick that I used was two have two "flip
buffers" which were
dedicated for each serial port. One buffer would be filled by the
interrupt handler, while the other would be buffer would be processed
by the bottom half (read: software interrupt) handler. When the
bottom half handler had emptied one buffer, it would check to see if
there were any characters in the other buffer, and if so, flip the two
and process the characters in that buffer.
I'm pretty sure SGI used a similar approach for networking packets.