11 Jan
2020
11 Jan
'20
6:30 a.m.
On Fri, 10 Jan 2020 at 17:19, Adam Thornton <athornton(a)gmail.com> wrote:
A) The original WD UART chip had very limited
buffering. The timing was
such that as high rates it could not empty accept a second character
without the first being overwritten. This was a long-standing issue for
many UARTs long in the 1990s. The original chip NS built and IBM used on
the PC (the NS8250) was notorious for the same problem. By the time of
Motorola's 6881, it had 8 characters of buffering IIRC.
Great, now I'm having flashbacks to upgrading my 4-port serial card with
16450s and then 16550s in the early 90s.
Yep, same sorts of memories here. I recall the 16450 upgrade being a big
deal for Internet connectivity in that a PC lacking the extra bytes of
buffering in the UART would find that the 80386 was having clock cycles
eaten nearly completely by PPP connections.
It was amazing to realize how a few bytes of memory lurking in a crucial
system interface could affect performance in such dramatic ways.
Tagged command queueing on SCSI controllers had a slightly less dramatic
effect on I/O performance, but again, a few hundred bytes of memory in the
right spot could nevertheless have dramatic effects.