19 May
2024
19 May
'24
4:41 p.m.
Hi,
Doug wrote:
The underlying evil of buffered IO still lurks. The
justification is
that it's necessary to match the characteristics of IO devices and to
minimize system-call overhead. The former necessity requires the
attention of hardware designers, but the latter is in the hands of
programmers. What can be done to mitigate the pain of border-crossing
into the kernel?
Has there been any system-on-chip experimentation with hardware ‘pipes’?
They have LIFOs for UARTs. What about LIFO hardware tracking the
content of shared memory?
Registers can be written to give the base address and buffer size.
Various water marks set: every byte as it arrives versus ‘It's not worth
getting out of bed for less than 64 KiB’. Read-only registers would
allow polling when the buffer is full or empty, or a ‘device’ could be
configured to interrupt. Trying to read/write a byte which wasn't
‘yours’ would trap.
It would be two cores synchronising without the kernel thanks to
hardware.
--
Cheers, Ralph.