6 Jun
2014
6 Jun
'14
12:26 a.m.
On Jun 5, 2014, at 11:07 AM, Clem Cole <clemc(a)ccc.com> wrote:
We had quite the panic figuring out what it was and
then forced field service to ensure all CPU cards were matched -- what a pain in the
tuckus. With the 5000 when we went full SMP, we screamed at Moto and got them to clean
up their act so that what was dumped on the stack could be restarted on any '020
regardless of stepping/microcode etc.
Sounds like our fun with Intel and their i860 RISC chips. Every chip stepping
had it's own "INTEL PROPRIETARY" errata which had fun things like "A
store followed by any number of instructions and then a load from the same location may
...." I loved the fact that Intel didn't think it was a good idea to tell
people what they had to do to make the chips work. Even when we got the Errata, they
were sometimes wrong. I spent a lot of time when stuck calling my contact at the
factory and making discrete inquiries which led to things like:
Intel: Remember those two NOP instructions we told you to put at the beginning of the
ISR?
Me: Yes, but the errata sheet says that ceased to be necessary after the B2 stepping
of the chip.
Intel: Well put them back and perhaps five or six more.
Of course they weren't as bad as dealing with some aspects of IBM at the time.
Me: There's a bug in the driver for this card.
IBM: That's not possible, it's product.
Oh, excuse me....there can't possibly be problems in the released product.