26 Aug
2020
26 Aug
'20
10:14 p.m.
You're right. Modes 2 and 3 are post-increment and post-increment deferred.
4 and 5 are pre-decrement and pre-decrement deferred.
On Wed, Aug 26, 2020 at 12:00 PM Noel Chiappa <jnc(a)mercury.lcs.mit.edu>
wrote:
From: John
Cowan
That's always true on the PDP-11 and Vax ...
because the processor
architecture (which has pre-increment and post-decrement
instructions,
but not their counterparts)
After Doug's message, I carefull re-read this, and I'm not sure it's
correct?
The PDP-11 has pre-decrement and post-increment, not the other way around
(as
above) - unless I'm misunderstanding what you meant by those terms?
That's why:
*p++ = 0;
turns (if p is in R2) into
CLR (R2)+
R2 is used, and then incremented after it has been used.
Noel