[TUHS] dmr streams & networking [was: Re: If not Linux, then what?]
clemc at ccc.com
Sun Sep 1 05:03:46 AEST 2019
On Sat, Aug 31, 2019 at 1:38 AM Dave Horsfall <dave at horsfall.org> wrote:
> Yep, that certainly rings a bell. ISTR that Sun had a board with the two
> CPUs, one keeping an eye on the other.
Interesting, I was under the belief that Sun never even tried the trick (at
least as a product). The original Stanford University Network (SUN) CPU
was built for an Intel Multibus (electrically and mechanically) but using a
single 68000 instead of an Intel processor. The 'SUN' was designed by one
of Forest's graduate students (Andy Bechtolsheim
<https://en.wikipedia.org/wiki/Andy_Bechtolsheim>); and the University licensed
the design extremely cheaply throughout the valley (VLSI Tech, *a.k.a.* Sun
Microsystems, was only one of the licensees. But for instance the original
Cisco AGS and the Imagen Laser printers both used CPU's licensed from the
FWIW: I knew Andy at CMU previously, he had designed a similar board for
the CMU front-end as I was leaving for Tektronix - when I was there we used
LSI-11s and Andy replaced that with an 8085 (then 8086) based Multibus
[IIRC, Phil Karn may have mixed up in all that too - he was hacking on what
would become KA9Q TCP on his Z80 and then the 8085. We had all taken the
graduate realtime course from Steely Dan as lab partners and our big
project was based on hacks to that hardware].
That said, it was Forest that proposed the executor/fixer trick (as I say
he gave a paper at an Asilomar Microprocessor Conference which I have sadly
misplaced). It is certainly possible that Andy tried building it, but the
only two firms that I know of that built processors using the idea were
Apollo and Masscomp (neither who used or licensed the SUN CPU design from
Stanford) although all of them used a flavor of the Multibus as their first
I don't know what Apollo did. The multibus mechanically had two connectors,
but the Intel-defined I/O bus was on the lower (larger connector). At,
Masscomp the MC-500 a private (synchronous) memory bus, that was very
similar to the BI in its protocol (because Dave designed both of course).
It was built on the unused/undefined header and ran much faster than the
I/O bus since memory fetches occurred. Also, the Masscomp >>card cage<<
was larger than Multibus (I think Apollo was also). The shorter boards
fit into the backplane, the larger size allowed for more 'chips to fit.'
IIRC, with the original memory chips being used at the time, one reason why
the Masscomp was so much faster than the Sun-1 (and 2) was it had larger
memory capacity on its boards and the memory transaction were quicker.
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