[TUHS] Why did PDPs become so popular?
stewart at serissa.com
Sat Dec 30 12:19:41 AEST 2017
(Both the ADU and the DECstation front end ran OSF-1 or Ultrix, which was unix-y, although the ADU itself did run VMS as a second OS :) )
If I remember correctly, the OS running on the ADU itself had what we would now call paravirtualized drivers - they just handed off packets or disk block I/Os to the I/O service program running on the DECStation. The ADU device drivers just managed ring buffers of requests, rather than raw SCSI commands destined for the real I/O devices.
PALcode is an Alpha thing, so that code running in PAL mode was responsible for things like TLB loads that might be different from model to model. Anything that was too expensive to implement in hardware or too infrequent to bother with got punted to PAL. PALcode was just ordinary Alpha assembler code, sometimes written in C I imagine, but it had to be very careful not to cause any faults or traps that required PALcode to implement.
The EV3 was an early Alpha chip, in, I think, .9 micron CMOS, that did not have an FPU, so the floating point was emulated. The first products were 200 MHz EV4 machines that were in .75 micron CMOS.
The 3 and 4 refer to Digital code names for CMOS processes. The EV stands for “Electric Vlasic” because the chip design team was fond of sticking nails into dill pickles and plugging them into the wall. The pickles could be seen to glow in a dark room before starting to smoke.
Ken Olsen came to visit the lab and wanted to know why we had christmas tree lights decorating the ADU chassis. We explained it was a safety feature, to remind people the power was on. 400 amps was nothing to fool around with. No wedding rings allowed in the lab.
> On 2017, Dec 29, at 8:47 PM, Kevin Bowling <kevin.bowling at kev009.com> wrote:
> That is awesome, thanks for the story and link. Enlightening to read
> about how the coherence protocol was developed in software. How was
> the ISA, and I assume even implementation detail, kept equal or close
> enough to the eventual microprocessor parts? Does the "Privileged
> Architecture Library" mean it was effectively microcoded? What kind
> of software structure was used to provide the I/O channel on the
> DECStations, for instance did it map the other TURBOChannel devices
> into the demo's address space so it ran the stock device drivers, or
> was the I/O server software intermediating a mailbox for doing SCSI,
> Ethernet etc with a different device model?
> Reminds me of a book I really liked "The Supermen: The Story of
> Seymour Cray and the Technical Wizards Behind the Supercomputer",
> especially Seymour Cray's willingness to throw out convention and
> redefine the game. Corollary to Larry's point about CPU designers
> losing by only competing against their own last design.. you can
> either make new markets or lead in the ongoing one, not a lot of air
> outside that.
> On Fri, Dec 29, 2017 at 5:54 PM, Lawrence Stewart <stewart at serissa.com> wrote:
>> I'll chime in just to say that designing with ECL was one hell of a lot of
>> fun compared to TTL.
>> The first Alpha chip (EV3) had pad drivers that could be configured for TTL
>> levels or for ECL levels. In fact, a good chunk of the ISSCC paper is about
>> the pad driver.
>> I was part of the team that built the first Alpha machine, the Alpha
>> Demonstration Unit, see
>> For a limited number of machines, with power no object we were able to make
>> an unabashed ECL design using the ECL 100K logic family, the ECLinPS family
>> (300 ps gate delays) and some custom Gigabit Logic Gallium Arsenide parts
>> for the memory board address line drivers.
>> We got power supply cables from a local valley welding shop and had them cut
>> to length. The shop owner wanted to know “what kind of a welder needs 18”
>> cables?” The issue was the 400 Amps of -4.5 v. Each jelly bean chip was
>> between 1/2 and 1 watt IIRC.
>> The beauty of ECL is that it is perfectly happy to drive 50 ohm transmission
>> lines, with shunt termination. This gives you incident wave switching and
>> really beautiful signal integrity. I think if Cray had tried to build the
>> Cray 1 with anything other than ECL it just would never have worked
>> reliably, especially with such long wires needed.
>> Essentially, ECL let you build big machines with the same reliability that
>> could only be achieved with small machines using TTL. Great stuff if you
>> can afford the power consumption.
>> In the same way that it is worthwhile to own a sports car at least once in
>> your life, it was a joy to build an ECL design.
>> On 2017, Dec 29, at 6:54 PM, Kevin Bowling <kevin.bowling at kev009.com> wrote:
>> I trust your judgement and experience WRT the Alpha.
>> If you're looking for massive performance deltas, what about ECL
>> designs like the IBM 3090 and Cray designs in the late '80s/ early
>> '90s? I believe those were not a multiple but a magnitude faster than
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