The first Alpha chip (EV3) had pad drivers that could be configured for TTL levels or for ECL levels. In fact, a good chunk of the ISSCC paper is about the pad driver.
I was part of the team that built the first Alpha machine, the Alpha Demonstration Unit, see
For a limited number of machines, with power no object we were able to make an unabashed ECL design using the ECL 100K logic family, the ECLinPS family (300 ps gate delays) and some custom Gigabit Logic Gallium Arsenide parts for the memory board address line drivers.
We got power supply cables from a local valley welding shop and had them cut to length. The shop owner wanted to know “what kind of a welder needs 18” cables?” The issue was the 400 Amps of -4.5 v. Each jelly bean chip was between 1/2 and 1 watt IIRC.
The beauty of ECL is that it is perfectly happy to drive 50 ohm transmission lines, with shunt termination. This gives you incident wave switching and really beautiful signal integrity. I think if Cray had tried to build the Cray 1 with anything other than ECL it just would never have worked reliably, especially with such long wires needed.
Essentially, ECL let you build big machines with the same reliability that could only be achieved with small machines using TTL. Great stuff if you can afford the power consumption.
In the same way that it is worthwhile to own a sports car at least once in your life, it was a joy to build an ECL design.
-Larry
I trust your judgement and experience WRT the Alpha.
If you're looking for massive performance deltas, what about ECL
designs like the IBM 3090 and Cray designs in the late '80s/ early
'90s? I believe those were not a multiple but a magnitude faster than
contemporaries.
Regards,