expression-1<offset-expr, size-expr, padding-expr>

[...] padding-expr controls the value used to pad the high order bits:  if even, zero-padded, if odd, one-padded.

I always wondered how this would work on the IBM S/360/370 architecture.  It is big-endian and bit 0 of a machine word is the most significant bit, not the least significant as in DEC's architectures.

Offset and Size taken as numbers of bits in a value (machine word), not bit numbers, works just fine for any architecture.  The PDP-10 and other DEC architectures before the PDP-11 were word-addressed with bit 0 at the high-order end.

The optional 3rd parameter is actually 0 for unsigned (zero) extension and 1 for signed (highest order bit in the extracted field) extension.  I don't think signed extension is widely used, but it depends on the data structure you're using.

When verifying that, I found something I did not remember, that in BLISS-16 and -32 (and I would guess also -64), but not -36 (the word-addressed PDP-10), one could declare 8-bit signed and unsigned data:

OWN
    X: BYTE SIGNED,
    Y: BYTE;

So the concepts of 'type' in BLISS, at least regarding data size and representation, can get a little complicated (not to be confused with COMPLEX :-) ).

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An aside re: bit twiddling from CMU and hardware description languages:

Note that the ISP/ISPL/ISPS machine description language(s) from books by Gordon Bell et al. used the following syntax for a bit or a bit field of a register:

REG<BIT_NR>
REG<HIGH_BIT_NR:LOW_BIT_NR>
REG<BIT_NR,BIT_NR,...>

(',...' is meta syntax.)  Sign extension was handled by a unary operator because the data were all bit vectors, instead of values as in BLISS, so the width (in bits) of an expression was known.  The DECSIM logic simulator inherited this syntax.  Brackets were used for memory addresses, so you might have M[0]<0:2> for the first 4 bits of the first word in memory.  I still find it the most clear syntax, but then it is what I used for many years.  (Sorry, VHDL and Verilog, although you won due to the idea back in the day that internally-developed VLSI CAD software was to be kept internal.)

- Aron