Addressing Modes & CPU Internals

1  Introduction

2  Instruction Addressing Modes

2.1  Absolute Jump

PC <- literal value in instruction

2.2  Relative Jump (Branch)

PC <- old PC + literal value in instruction

2.3  Register Indirect Jump

PC <- Rn

3  Data Addressing Modes

3.1  Immediate Addressing

ADD Dest, Src1, literal value

3.2  Register Mode

ADD Dest, Src, Register

3.3  Absolute or Direct Mode

ADD Dest, Src, memory address

3.4  Register Indirect Mode

ADD Dest, Src, (Register)

3.5  Indexed Absolute Mode

ADD Dest, Src, base(Register)

3.6  Base plus Offset Mode

ADD Dest, Src, BaseRegister(offset)

3.7  Base plus Index Mode

ADD Dest, Src, BaseRegister(IndexRegister)

3.8  Base plus Index plus Offset Mode

ADD Dest, Src, BaseRegister(IndexRegister)offset

3.9  Register Pre-increment/Pre-decrement Mode

ADD Dest, Src, +Register or -Register

3.10  Register Post-increment/Post-decrement Mode

ADD Dest, Src, Register+ or Register-

3.11  Memory Indirect Mode

ADD Dest, Src, (memory address)

4  Implementation Issues of Addressing Modes

5  How the CPU Works

6  Sequential Circuits

6.1  Phases of Each Instruction

7  CPU Operation: Issues

7.1  The Address Bus

7.2  The Data Bus

7.3  The Program Counter

7.4  The ALU


7.5  The Register File

7.6  Branch Logic

7.7  The Instruction Register

8  Hardwired Control Logic

9  Microcode Logic

9.1  Implementing the Microcode Logic

File translated from TEX by TTH, version 3.85.
On 12 Jan 2012, 15:50.