Question One

1. To perform the MIPS instruction   lw $t1, 300($t2)  the CPU will need to make:
   1. no memory accesses across the data bus.
   2. one memory access across the data bus.
   3. two memory accesses across the data bus.
   4. three memory accesses across the data bus.
   Comment: First the instruction has to be fetched from memory into the IR. Next, the address $t2+300 has to placed on the address bus, so the data at that memory location can be loaded into the $t1 register. Thus, two memory accesses.
2. The purpose of a stack frame is:
   1. to provide a push/pop stack data structure for a function to deal with any amount of user input.
   2. to hold the arguments, local variables, spilled registers and the return address for the currently executing function.
   3. to hold the current value of the program counter while a function is executing.
   4. to map part of the program's address space to RAM.
3. The Intel IA-32 architecture has pages, each 4,096 bytes in size. Part of the page map for the currently running process is this:

   Page Number	Page Frame	Modified	Accessed	User/Kernel	Read/Write	(In)Valid
   28	4	yes	yes	kernel	read-only	valid
   29	13	no	yes	user	read-only	valid
   30	19	yes	yes	user	read-write	valid

   Using the above information, choose the correct answer.
   1. The page starting at address 118,784 is mapped to the frame starting at address 49,152, which is a read-only kernel page.
   2. The page starting at address 122,880 is mapped to the frame starting at address 77,824, which is a read-write user-mode page.
   3. The page starting at address 16,384 is mapped to the frame starting at address 114,686, which is a read-only user-mode page.
   4. The page starting at address 4,096 is mapped to the frame starting at address 53,248, which is an invalid read-write kernel page.
   Comment: We multiply pages numbers by 4,096 to get their starting address. So page 28 is address 114,688. Page 29 is address 118,784. Page 30 is address 122,880. These pages map to page frames 4 (address 16,384), 13 (53,248) and 19 (77,824).
   Knowing these numbers, we can see that option b) is the right answer.
4. An exception is caused by:
   1. a specific machine instruction such as the MIPS syscall instruction.
   2. an electrical signal from a peripheral arriving on one of the CPU's interrupt lines.
   3. the CPU copying the contents of one general-purpose register into another general-purpose register.
   4. a user-mode instruction which attempts to perform a kernel-only action.
5. A CPU whose control logic is defined by a table stored inside the CPU is known as a:
   1. table-driven CPU.
   2. microcoded CPU.
   3. hardwired CPU.
   4. control logic CPU.

Question Two

1. Is this ISA a CISC or RISC architecture?
2. What is the maximum number of general purpose registers?
3. What is the data bus size for the CPU?
4. What is the address bus size for the CPU?
5. What is the maximum number of instructions in this ISA?
6. For each instruction format, how many operands does it have?
7. What is the size of each general purpose register, in bits?
8. Which instruction format would be used to:
   1. subtract one register from another?
   2. jump to the first instruction in a function?
   3. branch if the last ALU result was zero?
   4. increment a register value by 12?

Answers to Question Two

1. I'd say a CISC architecture as there are three instruction formats each of different length: 8 bits, 16 bits and 24 bits. RISC architectures usually use a single fixed-width instruction, typically one word long.
2. The Register fields are 2 bits, so that would indicate 4 registers (numbered 00, 01, 10, 11).
3. The largest literal value is 16 bits, so I would expect the registers to be able to hold these values. And assuming that the registers can also load/store to/from memory, that would make the data bus 16 bits wide, too. Some people argued 8 bits here, as the instructions are sized in groups of 8, so that was also a reasonable choice.
4. The Address field is 16 bits, so I would expect the address bus to be 16 bits wide, too.
5. The first instruction format has 3 opcode xxx bits, so max 8 here. The second has 4 opcode xxxx bits, so 16 max. Ditto the last format, so altogether 8+16+16 = 40 instructions max.
6. 1st format has two operands, both registers. 2nd format has two operands, a register and a literal value. 3rd format has two operands, a register and an address or literal value.
7. The largest literal value is 16 bits, so I would expect the registers to be able to hold these values. Registers are also usually the same size as the data bus.
8.  
   1. 1st format, as it has 2 register operands
   2. 3rd format, as it has an address operand
   3. Either 2nd or 3rd format, as both have a literal value which can be used to calculate PC+offset for the branch
   4. The value 12 fits into 8 bits, so 12 would fit into the literal field in the 2nd format.

Question Three

• Create a suitable stack frame for the function.
• Preserve the caller function's registers.
• Loop to process the String.
• Logic to count matching characters.
• Return the count, along with stack cleanup.

Answer to Question Three

	.data
string:	.asciiz "Hello everyone, here we are today."
	
	.text
main:	# Load $a0 with the string's address
	la $a0, string
	# Load $a1 with the character
	li $a1, 'e'
	# Count the letters
	jal letcount
	# Print the result
	move $a0, $v0
	li $v0, 1
	syscall 
	li $v0, 10
	syscall
	
# Function to count the number of
# letters in a string. $a0 holds
# the base address of the string,
# $a1 holds the letter to search for.
# $v0 returns with the count.
letcount:
	# Build a stack frame
	subu $sp, $sp, 24
	sw $ra, 20($sp)
	# Save $t0 on the stack frame.
	# $t0 will hold each character
	sw $t0, 0($sp)
	
	# Set the count to 0
	li $v0, 0
loop:	# Get the character at $a0
	# Stop if the character is NUL
	lb $t0, ($a0)
	beqz $t0, return
	
	# If the characters don't match
	# go off to move to next char
	bne $t0, $a1, incr
	# Otherwise increment the counter
	add $v0, $v0, 1
	
incr:	# Move $a0 up to next address
	add $a0, $a0, 1
	b loop
	
return:	# Restore $t0
	lw $t0, 0($sp)
	# Remove frame, return
	addu $sp, $sp, 24
	jr $ra

Question Four

1. Copy X register's value into Y register.
2. Add X and Y's value and store in the A register.
3. Add X and A's value and store in the A register.
4. Load the A register with the value in memory location X + 300.
5. Save the X register into memory location Y + 10.
6. If A is bigger than X, jump to the instruction at address 5,000.
7. Load the Y register with the value in memory location 128.
8. Set the Immediate register to the value 0.

Answers to Question Four

1. X can't be copied into Y. X goes thru the MUX into the ALU, but the ALU's output only goes into a MUX back into the A register, not to the Y register.
2. X+Y can't be done, as the second operand to the ALU is always the A register.
3. A= X+A can be done. X and A can be the operands to the ALU, and the ALU value can be written back into the A register.
4. X+300 can be calculated with the + unit and sent to the multiplexer onto the address bus. The data bus in goes into the A register via a multiplexer, so yes we can do this instruction.
5. Save the X register into memory location Y + 10 cannot be done. X's value cannot be placed onto the data bus out, so it cannot be saved into memory.
6. Yes. We can compare A and X with the ALU. Assuming that the immediate register is loaded with the literal value 5,000 from the instruction, then its value can be loaded into the PC, causing it to jump to that location with the next instruction.
7. Hard to tell with this one. X would have to be zero here. We can use immediate + X as an address, and Y can be loaded from the data bus in, but if X wasn't zero then the immediate + X value would not be 5,000.
8. Yes. Assuming the instruction has 0 in a literal field, the immediate register can be loaded from the instruction via the IR.