One of the main functions of an OS is to control all the I/O devices: disks, tapes clocks, terminals, network devices etc.
The OS must issue commands to the devices, catch interrupts and handle errors.
The OS must provide an interface between the devices and the users that is simple and easy to use.
If possible, the OS should make this interface device-independent.
The reasons for this all: the user doesn't want to worry about physical attributes of devices, their programming quirks, and how to handle errors.
Leaving this to the OS makes the users' lives easier, and allows scheduling algorithms to be created for the devices.
interrupt: 1. [techspeak] n. On a computer, an event that interrupts normal processing and temporarily diverts flow-of-control through an ``interrupt handler'' routine. See also trap. 2. interj. A request for attention from a hacker. Often explicitly spoken. ``Interrupt - have you seen Joe recently?''
interrupts locked out: When someone is ignoring you. In a restaurant, after several fruitless attempts to get the waitress's attention, a hacker might well observe ``She must have interrupts locked out''. The synonym `interrupts disabled' is also common.
We first must look and see how the OS `sees' the devices.
The CPU has three buses (lines of communication):
The address bus (holds the address it is accessing). Its size indicates how much memory the CPU can access. The data bus (data being read to/from that address). Its size indicates the natural data size for the machine. The status bus (indicates the address access and state of hardware).
Each device controller has a decoder which tells the device if the asserted address belongs to that device. If so, parts of the address and the data is written to/from the device.
Usually, this means that the device controller is mapped into the computer's memory:
On some other machines, a different (but equivalent) method of accessing the device controllers is used.
In the diagram, the UART controller decodes addresses 0xc000 to 0xc01f, 32 addresses.
It ignores addresses outside this region, and the decodes passes values 0x00 to 0x1f to the controller, when the address is inside the region.
Assume this UART uses the following addresses:
0 (0xc000): 1-byte wide, output format (Speed, parity, stop bits) 1 (0xc001): 1-byte wide, the output character 2 (0xc002): 1-byte wide, input format (Speed, parity, stop bits) 3 (0xc003): 1-byte wide, the input character
These special addresses are known as device registers, and are similar to the registers inside a CPU.
To output a character, first the OS must set up the output characteristics:
CPU asserts the address 0xc000 It places the data onto the data bus It asserts `write' on the r/w line It waits a period of time If no `valid address' returned, error
Then, to output a character, it is sent to 0xc001 as above.
Input from a device is more complicated. There are three types: polling, interrupts, and direct memory access.
With polling, the UART leaves the input character at the address 0xc003. The CPU must periodically scan this address to collect the character.
With interrupts, when a character arrives, the UART asserts its interrupt line. If the interrupt has priority greater than any other asserted interrupt line, the CPU stops what it is doing, and jumps to an interrupt handler for that line.
Here, the handler will collect the character, do something with it and return to what it was doing.
If the interrupt priority was too low, it will remain asserted until the other interrupts finish, and the CPU can handle it.
poll: v.,n. 1. [techspeak] The action of checking the status of an input line, sensor, or memory location to see if a particular external event has been registered. 2. To repeatedly call or check with someone: ``I keep polling him, but he's not answering his phone; he must be swapped out.''
Using polling or interrupts to transfer one byte is very expensive for large amnounts of data.
A better method is to use direct memory access ( DMA) which transfers lots of data without involving the CPU.
This requires some intelligence in the device controller.
For example, a disk drive controller has the following registers:
[tabbing271]
Imagine the OS wants to write one disk block (say 1,024 bytes) from address Ox3000 to track 159, sector 5.
The OS writes value Ox3000 into address Oxcf04, and the tuple `tk 159, sc 5, write' into address Oxcf00.
The device controller then uses the address/data bus to read the 1,024 bytes from main memory. It asserts address, and can thus temoprarily stop the CPU from accessing the bus.
However, it leaves the CPU free to do other operations.
When the DMA is complete, the disk controller sends an interrupt to inform the CPU that the DMA is complete.
Similarly, reads from the disk can be performed without supervision from the OS/CPU.