op1 | op2 | Rd | Rs |
2 | 2 | 2 | 2 |
op1 | op2 | Rd | Rs | immediate |
2 | 2 | 2 | 2 | 8 |
op1 | op2 | Mnemonic | Purpose |
00 | 00 | AND Rd, Rs | Rd = Rd AND Rs |
00 | 01 | OR Rd, Rs | Rd = Rd OR Rs |
00 | 10 | ADD Rd, Rs | Rd = Rd + Rs |
00 | 11 | SUB Rd, Rs | Rd = Rd - Rs |
01 | 00 | LW Rd, (Rs) | Rd = Mem[Rs] |
01 | 01 | SW Rd, (Rs) | Mem[Rs] = Rd |
01 | 10 | MOV Rd, Rs | Rd = Rs |
01 | 11 | NOP | Do nothing |
10 | 00 | JEQ Rd, immed | PC = immed if Rd == 0 |
10 | 01 | JNE Rd, immed | PC = immed if Rd != 0 |
10 | 10 | JGT Rd, immed | PC = immed if Rd > 0 |
10 | 11 | JLT Rd, immed | PC = immed if Rd < 0 |
11 | 00 | LW Rd, immed | Rd = Mem[immed] |
11 | 01 | SW Rd, immed | Mem[immed] = Rd |
11 | 10 | LI Rd, immed | Rd = immed |
11 | 11 | JMP immed | PC = immed |
op1 | op2 | instruct | pcsel | pcload | irload | imload | rw | dwrite | jumpsel | addrsel | regsel | dreg | sreg | aluop |
xx | xx | all | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | x | x | x | x |
op1 | op2 | instruct | pcsel | pcload | irload | imload | rw | dwrite | jumpsel | addrsel | regsel | dreg | sreg | aluop |
0x | xx | all | x | 0 | 0 | 0 | 0 | 0 | 0 | 0 | x | x | x | x |
1x | xx | all | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | x | x | x | x |
op1 | op2 | instruct | pcsel | pcload | irload | imload | rw | dwrite | addrsel | regsel | dreg | sreg | aluop |
00 | 00 | AND Rd, Rs | x | 0 | 0 | 0 | 0 | 1 | x | 3 | Rd | Rs | op2 |
00 | 01 | OR Rd, Rs | x | 0 | 0 | 0 | 0 | 1 | x | 3 | Rd | Rs | op2 |
00 | 10 | ADD Rd, Rs | x | 0 | 0 | 0 | 0 | 1 | x | 3 | Rd | Rs | op2 |
00 | 11 | SUB Rd, Rs | x | 0 | 0 | 0 | 0 | 1 | x | 3 | Rd | Rs | op2 |
01 | 00 | LW Rd, (Rs) | x | 0 | 0 | 0 | 0 | 1 | 2 | 2 | Rd | Rs | x |
01 | 01 | SW Rd, (Rs) | x | 0 | 0 | 0 | 1 | 0 | 3 | x | Rd | Rs | x |
01 | 10 | MOV Rd, Rs | x | 0 | 0 | 0 | 0 | 1 | x | 1 | Rd | Rs | x |
01 | 11 | NOP | x | 0 | 0 | 0 | 0 | 0 | x | x | x | x | x |
10 | 00 | JEQ Rd, immed | 0 | j | 0 | 0 | 0 | 0 | x | x | Rd | x | op2 |
10 | 01 | JNE Rd, immed | 0 | j | 0 | 0 | 0 | 0 | x | x | Rd | x | op2 |
10 | 10 | JGT Rd, immed | 0 | j | 0 | 0 | 0 | 0 | x | x | Rd | x | op2 |
10 | 11 | JLT Rd, immed | 0 | j | 0 | 0 | 0 | 0 | x | x | Rd | x | op2 |
11 | 00 | LW Rd, immed | x | 0 | 0 | 0 | 0 | 1 | 1 | 2 | Rd | x | x |
11 | 01 | SW Rd, immed | x | 0 | 0 | 0 | 1 | 0 | 1 | x | Rd | x | x |
11 | 10 | LI Rd, immed | x | 0 | 0 | 0 | 0 | 1 | x | 0 | Rd | x | x |
11 | 11 | JMP immed | 0 | 1 | 0 | 0 | 0 | 0 | x | x | x | x | x |
00 (zero) | Immediate Register |
01 (one) | sbus, i.e. the source register |
10 (two) | datain bus |
11 (three) | ALU output |
00 (zero) | Program Counter |
01 (one) | Immediate Register |
10 (two) | sbus, i.e the source register |
11 (three) | dbus, i.e the source register |
op1op2 | Test | Zero | Negative |
1000 (JEQ) | Rd == 0 | 1 | x |
1001 (JNE) | Rd != 0 | 0 | x |
1010 (JGT) | Rd > 0 | 0 | 0 |
1011 (JLT) | Rd < 0 | x | 1 |
LI R1,0x00 # Set running sum to zero LI R0,0x80 # Start at beginning of list loop: LW R2, (R0) # Get the next number JEQ R2, end # Exit loop if number == 0 ADD R1, R2 # Add number to running sum LI R3, 0x01 # Put 1 into R3, so we can do ADD R0, R3 # R0++ JMP loop # Loop back end: SW R1, 0x40 # Store result at address 0x40 inf: JMP inf # Infinite loop
LI R1,0x00 | e4 00 |
LI R0,0x80 | e0 80 |
LW R2, (R0) | 48 |
JEQ R2, end | 88 0d |
ADD R1, R2 | 26 |
LI R3, 0x01 | ec 01 |
ADD R0, R3 | 23 |
JMP loop | ff 04 |
SW R1, 0x40 | d4 40 |
JMP inf | ff 0f |